1. Field of the Invention
The present invention relates to the field of semiconductor processing. More particularly, the present invention relates to a method of fabricating a semiconductor device with a replacement metal gate.
2. Description of the Prior Art
As the size of the integrated circuit devices continues to scale down, the polysilicon gate and the silicon dioxide insulating layer of a metal-oxide-semiconductor field effect transistor (MOSFET) structure have confronted with the physical limits of the materials themselves. To meet the demands of scalability, a high-k metal gate (HK/MG) process is introduced.
In a HK/MG fabrication approach, a dummy gate composed of amorphous silicon is formed over a sacrificial silicon oxide layer in contact with a single-crystal semiconductor region of a substrate. A pair of spacers is disposed on sidewalls of the dummy gate. Later, an interlayer dielectric (ILD) layer is deposited in a blanket manner and a chemical mechanical polishing (CMP) is performed to remove excess ILD layer and expose the dummy gate.
A dummy poly removal (DPR) process is then performed to remove the dummy gate from between the pair of spacers. The sacrificial silicon oxide layer may be cleared from the surface of the substrate as by a dry etch or a wet etch selective to the material of the sidewall spacers. This creates a gate trench between the spacers where a high-k dielectric layer is then formed. Thereafter, a replacement metal gate is formed in the gate trench between the spacers contacting the high-k dielectric layer underneath.
Typically, several thermal treatment steps or anneal processes may be performed before the DPR process, and these thermal treatment steps may transform the dummy gate from an amorphous state directly into a polycrystalline state, which arises problems when performing the DPR process. Polysilicon residue defects are observed near the line end of the gate trench because of the difficulty of completely cleaning the polycrystalline Si dummy gate.